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MC34151, MC33151 High Speed Dual MOSFET Drivers
The MC34151/MC33151 are dual inverting high speed drivers specifically designed for applications that require low current digital circuitry to drive large capacitive loads with high slew rates. These devices feature low input current making them CMOS and LSTTL logic compatible, input hysteresis for fast output switching that is independent of input transition time, and two high current totem pole outputs ideally suited for driving power MOSFETs. Also included is an undervoltage lockout with hysteresis to prevent erratic system operation at low supply voltages. Typical applications include switching power supplies, dc to dc converters, capacitor charge pump voltage doublers/inverters, and motor controllers. These devices are available in dual-in-line and surface mount packages. * Two Independent Channels with 1.5 A Totem Pole Output * Output Rise and Fall Times of 15 ns with 1000 pF Load * CMOS/LSTTL Compatible Inputs with Hysteresis * Undervoltage Lockout with Hysteresis * Low Standby Current * Efficient High Frequency Operation * Enhanced System Performance with Common Switching Regulator Control ICs * Pin Out Equivalent to DS0026 and MMH0026
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8 PDIP-8 P SUFFIX CASE 626 1 1 8 8 1 SO-8 D SUFFIX CASE 751 1 x = 3 or 4 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week 3x151 ALYW MC3x151P AWL YYWW
8
PIN CONNECTIONS
N.C. 1 2 3 4 (Top View) 8 7 6 5 N.C. Drive Output A VCC Drive Output B
Representative Block Diagram
VCC 6 + + + + Logic Input A 100k 2 Drive Output A 7 - 5.7V +
Logic Input A Gnd Logic Input B
ORDERING INFORMATION
Device MC34151D Package SO-8 SO-8 PDIP-8 SO-8 SO-8 PDIP-8 SO-8 Shipping 98 Units/Rail 2500 Tape & Reel 50 Units/Rail 98 Units/Rail 2500 Tape & Reel 50 Units/Rail 2500 Units/Rail
+ MC34151DR2 + Logic Input B 4 100k Drive Output B 5 MC34151P MC33151D MC33151DR2 MC33151P Gnd 3 MC33151VDR2
(c) Semiconductor Components Industries, LLC, 2000
1
April, 2000 - Rev. 1
Publication Order Number: MC34151/D
MC34151, MC33151
MAXIMUM RATINGS
Rating Power Supply Voltage Logic Inputs (Note 1.) Drive Outputs (Note 2.) Totem Pole Sink or Source Current Diode Clamp Current (Drive Output to VCC) Power Dissipation and Thermal Characteristics D Suffix SO-8 Package Case 751 Maximum Power Dissipation @ TA = 50C Thermal Resistance, Junction-to-Air P Suffix 8-Pin Package Case 626 Maximum Power Dissipation @ TA = 50C Thermal Resistance, Junction-to-Air Operating Junction Temperature Operating Ambient Temperature MC34151 MC33151 Storage Temperature Range Symbol VCC Vin IO IO(clamp) Value 20 -0.3 to VCC 1.5 1.0 Unit V V A
PD RJA PD RJA TJ TA
0.56 180 1.0 100 +150 0 to +70 -40 to +85
W C/W W C/W C C
Tstg
-65 to +150
C
ELECTRICAL CHARACTERISTICS (VCC = 12 V, for typical values TA = 25C, for min/max values TA is the only operating
ambient temperature range that applies [Note 3.], unless otherwise noted.) Characteristics LOGIC INPUTS Input Threshold Voltage - High State Logic 1 Input Threshold Voltage - Low State Logic 0 Input Current - High State (VIH = 2.6 V) Input Current - Low State (VIL = 0.8 V) DRIVE OUTPUT Output Voltage - Low State (ISink = 10 mA) Output Voltage - Low State (ISink = 50 mA) Output Voltage - Low State (ISink = 400 mA) Output Voltage - High State (ISource = 10 mA) Output Voltage - High State (ISource = 50 mA) Output Voltage - High State (ISource = 400 mA) Output Pull-Down Resistor SWITCHING CHARACTERISTICS (TA = 25C) Propagation Delay (10% Input to 10% Output, CL = 1.0 nF) Logic Input to Drive Output Rise Logic Input to Drive Output Fall Drive Output Rise Time (10% to 90%) CL = 1.0 nF Drive Output Rise Time (10% to 90%) CL = 2.5 nF Drive Output Fall Time (90% to 10%) CL = 1.0 nF Drive Output Fall Time (90% to 10%) CL = 2.5 nF TOTAL DEVICE Power Supply Current Standby (Logic Inputs Grounded) Operating (CL = 1.0 nF Drive Outputs 1 and 2, f = 100 kHz) Operating Voltage ICC - - 6.0 10.5 10 15 18 V mA ns tPLH(in/out) tPHL(in/out) tr tf - - - - - - 35 36 14 31 16 32 100 100 30 - 30 - ns ns VOL - - - 10.5 10.4 9.5 - 0.8 1.1 1.7 11.2 11.1 10.9 100 1.2 1.5 2.5 - - - - V VIH VIL IIH IIL 2.6 - - - 1.75 1.58 200 20 - 0.8 500 100 V A Symbol Min Typ Max Unit
VOH
RPD
k
VCC 6.5 - 1. For optimum switching speed, the maximum input voltage should be limited to 10 V or VCC, whichever is less. 2. Maximum package power dissipation limits must be observed. 3. Tlow = 0C for MC34151 Thigh = +70C for MC34151 -40C for MC33151 +85C for MC33151
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MC34151, MC33151
12 4.7 V 0.1 + 6 + + + Logic Input 50 + + 4 100k 5 tPHL 90% Drive Output 3 tf 10% tr 2 100k + - 5.7V 7 CL 5.0 V Logic Input tr, tf 10 ns 0V 90% 10% tPLH + Drive Output
Figure 1. Switching Characteristics Test Circuit
2.4 V th , INPUT THRESHOLD VOLTAGE (V) I in , INPUT CURRENT (mA) 2.0 1.6 1.2 0.8 0.4 0 0 2.0 4.0 6.0 8.0 Vin, INPUT VOLTAGE (V) 10 12 VCC = 12 V TA = 25C 2.2 2.0 1.8 1.6 1.4 1.2 1.0 -55
Figure 2. Switching Waveform Definitions
VCC = 12 V
Upper Threshold Low State Output
Lower Threshold High State Output
-25
0 25 50 75 TA, AMBIENT TEMPERATURE (C)
100
125
Figure 3. Logic Input Current versus Input Voltage
t PLH(IN/OUT) , DRIVE OUTPUT PROPAGATION DELAY (ns) 200 160 120 80 40 Vth(lower) 0 -1.6 -1.2 -0.8 -0.4 0 Vin, INPUT OVERDRIVE VOLTAGE BELOW LOWER THRESHOLD (V) VCC = 12 V CL = 1.0 nF TA = 25C Overdrive Voltage is with Respect to the Logic Input Lower Threshold t PHL(IN/OUT) , DRIVE OUTPUT PROPAGATION DELAY (ns) 200
Figure 4. Logic Input Threshold Voltage versus Temperature
Overdrive Voltage is with Respect to the Logic Input Lower Threshold 160 120 80 40 0
VCC = 12 V CL = 1.0 nF TA = 25C
Vth(upper) 0 1.0 2.0 3.0 4.0 Vin, INPUT OVERDRIVE VOLTAGE ABOVE UPPER THRESHOLD (V)
Figure 5. Drive Output Low-to-High Propagation Delay versus Logic Overdrive Voltage
Figure 6. Drive Output High-to-Low Propagation Delay versus Logic Input Overdrive Voltage
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V clamp , OUTPUT CLAMP VOLTAGE (V)
3.0 2.0 1.0
High State Clamp (Drive Output Driven Above VCC)
90% Logic Input
VCC = 12 V Vin = 5 V to 0 V CL = 1.0 nF TA = 25C
VCC = 12 V 80 s Pulsed Load 120 Hz Rate TA = 25C
VCC 0 0 Gnd -1.0 0 0.2 Low State Clamp (Drive Output Driven Below Ground) 1.2 1.4
10%
Drive Output
50 ns/DIV
0.4 0.6 0.8 1.0 IO, OUTPUT LOAD CURRENT (A)
Figure 7. Propagation Delay
Figure 8. Drive Output Clamp Voltage versus Clamp Current
V sat , OUTPUT SATURATION VOLTAGE(V)
-1.0 -2.0 -3.0 3.0 2.0 1.0 0 0 0.2
VCC
Source Saturation VCC = 12 V (Load to Ground) 80 s Pulsed Load 120 Hz Rate TA = 25C
V sat , OUTPUT SATURATION VOLTAGE(V)
0
0 -0.5 -0.7 -0.9 -1.1 1.9 1.7
Source Saturation (Load to Ground) VCC
Isource = 10 mA Isource = 400 mA
VCC = 12 V
Isink = 400 mA
Sink Saturation (Load to VCC)
Gnd 1.2 1.4
0.4 0.6 0.8 1.0 IO, OUTPUT LOAD CURRENT (A)
1.5 1.0 Isink = 10 mA 0.8 Gnd Sink Saturation 0.6 (Load to VCC) 0 -55 -25 0 25 50 75 TA, AMBIENT TEMPERATURE (C)
100
125
Figure 9. Drive Output Saturation Voltage versus Load Current
Figure 10. Drive Output Saturation Voltage versus Temperature
90%
90%
VCC = 12 V Vin = 5 V to 0 V CL = 1.0 nF TA = 25C
10%
VCC = 12 V Vin = 5 V to 0 V CL = 1.0 nF TA = 25C
10%
10 ns/DIV
10 ns/DIV
Figure 11. Drive Output Rise Time
Figure 12. Drive Output Fall Time
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MC34151, MC33151
80 t r -t f , OUTPUT RISE-FALL TIME(ns) ICC, SUPPLY CURRENT (mA) VCC = 12 V VIN = 0 V to 5.0 V TA = 25C 80 VCC = 12 V Both Logic Inputs Driven 0 V to 5.0 V 50% Duty Cycle Both Drive Outputs Loaded TA = 25C f = 500 kHz 20
60
60
f = 200 kHz
40
40
20
tf tr
f = 50 kHz
0 0.1
1.0 CL, OUTPUT LOAD CAPACITANCE (nF)
10
0 0.1
1.0 CL, OUTPUT LOAD CAPACITANCE (nF)
10
Figure 13. Drive Output Rise and Fall Time versus Load Capacitance
80 ICC , SUPPLY CURRENT (mA) 1 2 3 4 ICC , SUPPLY CURRENT (mA) Both Logic Inputs Driven 0 V to 5.0 V, 50% Duty Cycle Both Drive Outputs Loaded TA = 25C 1 - VCC = 18 V, CL = 2.5 nF 2 - VCC = 12 V, CL = 2.5 nF 3 - VCC = 18 V, CL = 1.0 nF 4 - VCC = 12 V, CL = 1.0 nF
Figure 14. Supply Current versus Drive Output Load Capacitance
8.0 TA = 25C 6.0 Logic Inputs at VCC Low State Drive Outputs
60
40
4.0 Logic Inputs Grounded High State Drive Outputs 2.0
20
0
10 k
100 f, INPUT FREQUENCY (Hz)
1.0 M
0
0
4.0
8.0 VCC, SUPPLY VOLTAGE (V)
12
16
Figure 15. Supply Current versus Input Frequency
Figure 16. Supply Current versus Supply Voltage
APPLICATIONS INFORMATION
Description Output Stage
The MC34151 is a dual inverting high speed driver specifically designed to interface low current digital circuitry with power MOSFETs. This device is constructed with Schottky clamped Bipolar Analog technology which offers a high degree of performance and ruggedness in hostile industrial environments.
Input Stage
The Logic Inputs have 170 mV of hysteresis with the input threshold centered at 1.67 V. The input thresholds are insensitive to VCC making this device directly compatible with CMOS and LSTTL logic families over its entire operating voltage range. Input hysteresis provides fast output switching that is independent of the input signal transition time, preventing output oscillations as the input thresholds are crossed. The inputs are designed to accept a signal amplitude ranging from ground to VCC. This allows the output of one channel to directly drive the input of a second channel for master-slave operation. Each input has a 30 k pull-down resistor so that an unconnected open input will cause the associated Drive Output to be in a known high state.
Each totem pole Drive Output is capable of sourcing and sinking up to 1.5 A with a typical `on' resistance of 2.4 at 1.0 A. The low `on' resistance allows high output currents to be attained at a lower VCC than with comparative CMOS drivers. Each output has a 100 k pull-down resistor to keep the MOSFET gate low when VCC is less than 1.4 V. No over current or thermal protection has been designed into the device, so output shorting to VCC or ground must be avoided. Parasitic inductance in series with the load will cause the driver outputs to ring above VCC during the turn-on transition, and below ground during the turn-off transition. With CMOS drivers, this mode of operation can cause a destructive output latch-up condition. The MC34151 is immune to output latch-up. The Drive Outputs contain an internal diode to VCC for clamping positive voltage transients. When operating with VCC at 18 V, proper power supply bypassing must be observed to prevent the output ringing from exceeding the maximum 20 V device rating. Negative output transients are clamped by the internal NPN pull-up transistor. Since full supply voltage is applied across
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MC34151, MC33151
the NPN pull-up during the negative output transient, power dissipation at high frequencies can become excessive. Figures 19, 20, and 21 show a method of using external Schottky diode clamps to reduce driver power dissipation.
Undervoltage Lockout
V GS , GATE-TO-SOURCE VOLTAGE (V)
An undervoltage lockout with hysteresis prevents erratic system operation at low supply voltages. The UVLO forces the Drive Outputs into a low state as VCC rises from 1.4 V to the 5.8 V upper threshold. The lower UVLO threshold is 5.3 V, yielding about 500 mV of hysteresis.
Power Dissipation
gate charge information on their data sheets. Figure 17 shows a curve of gate voltage versus gate charge for the ON Semiconductor MTM15N50. Note that there are three distinct slopes to the curve representing different input capacitance values. To completely switch the MOSFET `on', the gate must be brought to 10 V with respect to the source. The graph shows that a gate charge Qg of 110 nC is required when operating the MOSFET with a drain to source voltage VDS of 400 V.
16 MTM15N50 ID = 15 A TA = 25C VDS = 100 V 8.0 8.9 nF 4.0 2.0 nF 0 CGS = 40 80 Qg, GATE CHARGE (nC) 120 VDS = 400 V
Circuit performance and long term reliability are enhanced with reduced die temperature. Die temperature increase is directly related to the power that the integrated circuit must dissipate and the total thermal resistance from the junction to ambient. The formula for calculating the junction temperature with the package in free air is: TJ = TA + PD (RJA) where: TJ = Junction Temperature TA = Ambient Temperature PD = Power Dissipation RJA = Thermal Resistance Junction to Ambient There are three basic components that make up total power to be dissipated when driving a capacitive load with respect to ground. They are: PD = PQ + PC + PT PQ = Quiescent Power Dissipation PC = Capacitive Load Power Dissipation PT = Transition Power Dissipation The quiescent power supply current depends on the supply voltage and duty cycle as shown in Figure 16. The device's quiescent power dissipation is: where:
PQ = VCC ICCL (1-D) + ICCH (D)
12
Qg VGS 160
0
Figure 17. Gate-To-Source Voltage versus Gate Charge
The capacitive load power dissipation is directly related to the required gate charge, and operating frequency. The capacitive load power dissipation per driver is:
PC(MOSFET) = VC Qg f
where:
ICCL = Supply Current with Low State Drive Outputs ICCH = Supply Current with High State Drive Outputs D = Output Duty Cycle
The capacitive load power dissipation is directly related to the load capacitance value, frequency, and Drive Output voltage swing. The capacitive load power dissipation per driver is: where: PC = VOH = VOL = CL = f= VCC (VOH - VOL) CL f High State Drive Output Voltage Low State Drive Output Voltage Load Capacitance frequency
The flat region from 10 nC to 55 nC is caused by the drain-to-gate Miller capacitance, occurring while the MOSFET is in the linear region dissipating substantial amounts of power. The high output current capability of the MC34151 is able to quickly deliver the required gate charge for fast power efficient MOSFET switching. By operating the MC34151 at a higher VCC, additional charge can be provided to bring the gate above 10 V. This will reduce the `on' resistance of the MOSFET at the expense of higher driver dissipation at a given operating frequency. The transition power dissipation is due to extremely short simultaneous conduction of internal circuit nodes when the Drive Outputs change state. The transition power dissipation per driver is approximately:
PT 9 VCC (1.08 VCC CL f - 8 y 10-4) PT must be greater than zero.
When driving a MOSFET, the calculation of capacitive load power PC is somewhat complicated by the changing gate to source capacitance CGS as the device switches. To aid in this calculation, power MOSFET manufacturers provide
Switching time characterization of the MC34151 is performed with fixed capacitive loads. Figure 13 shows that for small capacitance loads, the switching speed is limited by transistor turn-on/off time and the slew rate of the internal nodes. For large capacitance loads, the switching speed is limited by the maximum output current capability of the integrated circuit.
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MC34151, MC33151
LAYOUT CONSIDERATIONS High frequency printed circuit layout techniques are imperative to prevent excessive output ringing and overshoot. Do not attempt to construct the driver circuit on wire-wrap or plug-in prototype boards. When driving large capacitive loads, the printed circuit board must contain a low inductance ground plane to minimize the voltage spikes induced by the high ground ripple currents. All high current loops should be kept as short as possible using heavy copper runs to provide a low impedance high frequency path. For optimum drive performance, it is recommended that the initial circuit design contains dual power supply bypass capacitors connected with short leads as close to the VCC pin and ground as the layout will permit. Suggested capacitors are a low inductance 0.1 F ceramic in parallel with a 4.7 F tantalum. Additional bypass capacitors may be required depending upon Drive Output loading and circuit layout. Proper printed circuit board layout is extremely critical and cannot be over emphasized.
VCC 47 0.1 6 + ++ - 5.7V + 7 100k 100k D1 1N5819 5 100k Vin + Rg Vin
+ 2
TL494 or TL594
+ + 4
3
The MC34151 greatly enhances the drive capabilities of common switching regulators and CMOS/TTL logic devices.
Series gate resistor Rg may be needed to damp high frequency parasitic oscillations caused by the MOSFET input capacitance and any series wiring inductance in the gate-source circuit. Rg will decrease the MOSFET switching speed. Schottky diode D1 can reduce the driver's power dissipation due to excessive ringing, by preventing the output pin from being driven below ground.
Figure 18. Enhanced System Performance with Common Switching Regulators
+ + 7 100k
Figure 19. MOSFET Parasitic Oscillations
+
4X 1N5819 + 5
+
Isolation Boundary
100k
100k
1N 5819
3 Output Schottky diodes are recommended when driving inductive loads at high frequencies. The diodes reduce the driver's power dissipation by preventing the output pins from being driven above VCC and below ground.
3
Figure 20. Direct Transformer Drive
Figure 21. Isolated MOSFET Drive
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MC34151, MC33151
Vin + + Rg(on) 100k 0 - + C1 Rg(off) 100k Base Charge Removal IB Vin
In noise sensitive applications, both conducted and radiated EMI can be reduced significantly by controlling the MOSFET's turn-on and turn-off times.
The totem-pole outputs can furnish negative base current for enhanced transistor turn-off, with the addition of capacitor C1.
Figure 22. Controlled MOSFET Drive
Figure 23. Bipolar Transistor Drive
VCC = 15 V 4.7 + 6 + - 5.7V + 2 100k 7 6.8 10 + 1N5819 47 + + VO 2.0 VCC 0.1
+ +
+
+ + 4 100k 330pF 5 6.8 10 +
1N5819 47
- VO - VCC +
3 10k
Output Load Regulation The capacitor's equivalent series resistance limits the Drive Output Current to 1.5 A. An additional series resistor may be required when using tantalum or other low ESR capacitors. IO (mA) 0 1.0 10 20 30 50 +VO (V) 27.7 27.4 26.4 25.5 24.6 22.6 -VO (V) -13.3 -12.9 -11.9 -11.2 -10.5 -9.4
Figure 24. Dual Charge Pump Converter
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MC34151, MC33151
PACKAGE DIMENSIONS
PDIP-8 P SUFFIX CASE 626-05 ISSUE K
NOTES: 1. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 2. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 9.40 10.16 6.10 6.60 3.94 4.45 0.38 0.51 1.02 1.78 2.54 BSC 0.76 1.27 0.20 0.30 2.92 3.43 7.62 BSC --- 10_ 0.76 1.01 INCHES MIN MAX 0.370 0.400 0.240 0.260 0.155 0.175 0.015 0.020 0.040 0.070 0.100 BSC 0.030 0.050 0.008 0.012 0.115 0.135 0.300 BSC --- 10_ 0.030 0.040
8
5
-B-
1 4
F
NOTE 2
-A- L
C -T-
SEATING PLANE
J N D K
M
M
H
G 0.13 (0.005) TA
M
B
M
SO-8 D SUFFIX CASE 751-06 ISSUE T
A
8
D
5
C
E
1 4
H
0.25
M
B
M
h B C e A
SEATING PLANE
X 45 _
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS ARE IN MILLIMETER. 3. DIMENSION D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E e H h L MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.35 0.49 0.19 0.25 4.80 5.00 3.80 4.00 1.27 BSC 5.80 6.20 0.25 0.50 0.40 1.25 0_ 7_
q
L 0.10 A1 B 0.25
M
CB
S
A
S
q
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Notes
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Notes
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